DRSSTC II

The first DRSSTC I pictured was a big one. I started winding the secondary before I had any reason to think I could drive it. About 2500 turns of 0.35 mm double-enamelled wire on a 100×16 cm PVC pipe. A month later it was obvious this should not be a first coil, so in April 2019 I put it aside and built DRSSTC I instead.

Once that smaller coil was running properly, I came back to this one.

Winding started on 1 April 2019 and took three days, about 20 hours. I was careful, and I still left a lot of imperfections in the winding. The double enamel is what I am counting on to keep a turn-to-turn flashover from starting there.

The pipe is tall enough that the rest of the coil had to be built around it, not the other way around.

In the summer of 2020 I picked the driver. By then I had found pulse-skipping. A normal OCD trips and shuts the bridge off. Pulse-skipping only drops primary cycles until the current falls back under the threshold, so the secondary keeps ringing and the primary current is not allowed to climb further. More energy into the arc, and a longer, hotter streamer, without a hard shutdown.

Philip Slawinski sells a UD+ that does this, at a sensible price. The notes are at classictesla.com/pslawinski/udplus.html. The board arrived and ran as delivered.

The primary is 10 mm copper pipe, 8 turns, on holders I printed for it. My brother David wound it with me.

Inside, it ended up tapped at 7.5 turns. Outside, that tap was wrong, which took a week to understand.

The topload is seven printed rings, 20 mm stock, wrapped in aluminium tape. With that on the secondary the resonance sits near 64 kHz. DRSSTC I is the small coil beside it.

The MMC is 14S2P of MPAPB1K2W22J0M6, 2.2 µF at 1.2 kV. The datasheet is at farnell.com/datasheets/2843159.pdf. They are robust, and the screw terminals are the right way to move this much current. Two more, in parallel, are the snubbers on the bridge. The screw holes happened to fit the IGBT terminals.

The stack lives on a printed holder. Same capacitors, three jobs: the MMC, the bridge snubbers, and a reminder that the mounting is part of the current path.

The switches are Semikron SKM400GB12E4 modules, bought on eBay for about 30 dollars each. The datasheet is at semikron.com/products/product-classes/igbt-modules/detail/skm400gb12e4-22892087.html. I wanted a seller with a reputation, and I found a German one with strong ratings, so there is a fair chance they are genuine. Gate capacitance measured about 27 nF, close to the datasheet. Good enough to build on.

The DC bus is 2S2P of 450 V, 10 000 µF capacitors: 10 000 µF at 900 V. A 22 kΩ, 50 W resistor across the primary terminals bleeds the MMC. Each gate charges through 4.7 Ω and discharges through a Schottky and the 1 Ω already in the module. A 27 V TVS sits across every gate.

At this bus an NTC is the wrong tool. Twenty-four 8.2 kΩ, 10 W resistors in parallel make about 340 Ω and 240 W, and that string charges the bus. After about 20 seconds a relay shorts the resistors out. Two relays, actually, in parallel, timed by an IRF3205 and a 220 µF capacitor. The coil must not be run while it is still on the resistors. A 5 mm green LED on the front panel is the sign that the relay has closed.

The soft start and the UD+ share a Mean Well 24 V, 5 A supply. The scope shot is inrush into a single 10 000 µF, 450 V capacitor, charging only to 120 V, 20 A per division, measured after the full-wave rectifier.

On DRSSTC I the gate-drive transformers and the current transformers were a guess. This time I did the sums first. Large ferrite cores, permeability low enough to deliver current, and big enough that they stay out of saturation even at 30 kHz, which is 20 kHz under the planned operating frequency. Each GDT is 10 turns of twisted wire, with two wires in parallel on the primary.

Feedback is two cascaded current transformers, 1:33 and 1:30, so 1:990 overall.

Once it was assembled I tapped the primary at 7.5 turns and started measuring. On 10 August 2021 the low-side gates were readable, and the primary current was a clean 54 kHz at 100 A per division, 350 µs on-time.

At 110 V AC, 350 µs, and a 350 A OCD, the discharge reached 75 cm. A ground strike the same week was about 80 cm.

The first time I took it outside, the arcs collapsed to under 10 cm. Same settings as the indoor runs, where it had been fine. Back inside, fine again. A solid secondary ground did not change the outdoor result. It took a week. Indoors the topload sees the ceiling, the mains wiring, and a lot of nearby earth, so its capacitance is much higher. Outdoors that extra capacitance is gone. The primary had to come down from 7.5 turns to 6.1.

After that retune, at about 180 V AC and a modest 400 A OCD, the arcs went past a metre. The duo shot is 350 µs, 180 V AC, 400 A, over 2 kVA, with DRSSTC I running beside it.

On 14 September 2021, during a duo run, something exploded. Loud, and short. The transistors were fine. What failed were the mains leads into the coil. I had forgotten the rating of that cable. It was nowhere near 15 A, which is what the coil was drawing. The insulation melted, the conductors touched, and the short was in the cable.

The coil itself was unharmed. I filmed the bang. The still of the leads is what was left of them.

Primary a little under the secondary, pulse-skipping instead of a hard OCD shutdown, and a soft start that has to finish before the coil is allowed to run.